Breaking Barriers: NanoIC Pilot Line Pushing the Limits of Beyond-2nm Chip Innovation

Revolutionizing Semiconductor Technology with the NanoIC Pilot Line

The NanoIC pilot line is setting its sights on becoming the premier R&D pilot line for beyond semiconductor technology worldwide. This initiative is aligned with the European Chips Act’s goal of strengthening Europe’s position in the global semiconductor ecosystem and driving innovation in critical sectors like computing, communication, mobility, energy, and health. By serving as a crucial link between cutting-edge research and practical applications, the NanoIC pilot line plays a pivotal role in solidifying Europe’s position at the forefront of semiconductor innovation and competitiveness.

A key challenge in the semiconductor industry is bridging the gap between research breakthroughs and commercialization. The NanoIC pilot line addresses this challenge by fostering innovation in computing system architectures through the development of specific semiconductor technologies. The ultimate objective is to empower European companies to lead the way in semiconductor innovation.

The NanoIC pilot line specializes in providing a beyond 2nm system-on-chip (SoC) pilot line for advancing and refining selected advanced logic, memory, and interconnect technologies. This project emphasizes large-scale capacity building, particularly at imec’s cleanroom in Leuven (Belgium), collaborative R&D efforts, maturation of advanced technologies for prototyping, and innovation support, enabling the entire semiconductor ecosystem to access these cutting-edge technologies. Participants can engage with the NanoIC pilot line according to their specific needs and innovation objectives, regardless of their position in the value chain. This approach provides early insights into emerging fields and supports Europe in maintaining competitiveness across the entire semiconductor value chain, from materials and equipment to designs and systems.

The NanoIC Consortium

Leading the NanoIC pilot line project consortium are imec, CEA-Leti in France, Fraunhofer-Gesellschaft (FhG) in Germany, VTT Technical Research Center in Finland, Tyndall National Institute in Ireland, and the Center for Surface Science and Nanotechnology of the University Politehnica of Bucharest in Romania. Supported by the Flemish Government, other participating states, and the Chips Joint Undertaking, these partners are collectively working towards the successful implementation of the pilot line.

Pioneering Future Compute Systems

Nanosheet class of logic devices is anticipated to drive scaling and performance through three additional generations (N2, A14, A10). The introduction of complementary field effect transistor (CFET) architectures around 2031 at the A7 node represents a significant milestone in CMOS device design. Advancements in this area necessitate extensive research into new materials, process modules, equipment, and advanced patterning capabilities, with high numerical aperture extreme ultraviolet (high NA EUV) lithography playing a crucial role.

In the realm of memory innovations, the focus is on novel magnetic memories, particularly spin orbit torque-magnetic random access memory (SOT-MRAM) and embedded Dynamic Random Access Memory (eDRAM). For the latter, an alternative 2T0C configuration is being developed, exploring semiconductors with wide bandgaps such as semiconducting oxides like indium-gallium-zinc-oxide or 2D transition metal dichalcogenides as promising alternative channel materials. Simultaneously, the development of a 3D memory platform to explore future memory options beyond SRAM and DRAM is essential to address memory capacity and bandwidth challenges posed by new workloads.

For integrating different dies into systems, advanced electrical and optical interconnects beyond 2nm are essential. To further enhance electrical interconnects, 3D heterogeneous integration techniques like die-to-wafer (D2W) hybrid bonding will be enabled. The NanoIC pilot line aims to achieve lines under 2µm for electrically connecting dies side-by-side and enabling 2.5D chiplet integration on a low-cost interposer platform, offering fine-pitch redistribution layer (FP RDL) technology based on copper line and via embedded in polymers.

The leading-edge logic, memory, and interconnect technologies defined at industry-relevant dimensions form the core focus of the NanoIC pilot line. Enabling these technologies entails evaluating new processes and materials, ensuring stringent process control, and having a diverse set of validation pathways. Establishing relevant process modules necessitates investing in entirely new processing and metrology tools capabilities. These modules serve as the foundational elements for the baseline flows and are subject to continuous improvements to enhance maturation, accelerate learning, and progress towards higher TRL levels. Stable baseline flows present opportunities for R&D collaboration, allowing materials and equipment vendors to stay at the forefront of innovation.

Facilitating Advanced Chip Design with Cutting-Edge PDKs

To assist European designers, whether in academia or industry, in exploring advancements in logic, memory, and interconnect technologies, the NanoIC pilot line offers early access to advanced process design kits (PDKs).

These comprehensive toolsets provide designers with predictive models, cell libraries, and system-level integration resources, enabling precise simulation and validation of integrated circuits for advanced technology nodes. By making these hands-on kits available, circuit designers can delve into upcoming chip architectures, tackle complex design challenges, and drive innovation in nodes beyond 2nm.

The NanoIC pilot line offers two complementary PDKs: pathfinding PDKs for early design exploration in cutting-edge lC technologies and system exploration PDKs to pave the way for hardware prototyping and system-level innovation.

These PDKs are rolled out throughout the project and encompass multiple versions of the N2 pathfinding PDK, including releases in A14 and A7 logic PDKs. Memory PDKs are aligned with progress in eDRAM and SOT-MRAM, while advanced interconnect solutions can be explored through RDL, silicon interposer, and D2W hybrid bonding.

Fostering Innovation in Europe

The NanoIC pilot line offers flexible access to advanced logic, memory, and interconnect technologies for the entire semiconductor ecosystem. Companies, research institutes, start-ups, and universities can collaborate based on their innovation requirements.

Integrated device manufacturers and foundries can leverage the baselines to explore new modules and performance enhancement options. Equipment and materials suppliers, both European and global, are encouraged to collaborate to enable advanced baselines for testing and refining new tools and processes. Furthermore, start-ups, universities, and design companies have access to the pathfinding PDK for early design exploration of future nodes and system exploration PDKs for hardware prototyping and system-level innovation. Additionally, the NanoIC pilot line is dedicated to nurturing the next generation of semiconductor experts. By partnering with the EU Competence Centers, we offer classroom and virtual courses on beyond 2nm technologies, covering semiconductor materials to SoC design. Our hands-on internships and learning programs provide students with real-world experience, while our industry-oriented training equips Bachelor’s, Master’s, and PhD students for future challenges. Through expert courses, technical training, and immersive bootcamps, the NanoIC pilot line is cultivating a skilled workforce to drive the European semiconductor industry forward.

In conclusion, the NanoIC pilot line is strategically positioned to bridge the gap between cutting-edge research and practical applications in the semiconductor industry. This project underscores Europe’s dedication to innovation, competitiveness, and sustainable growth in an increasingly digital landscape. By advancing technologies and fostering collaboration, the NanoIC pilot line aims to reinforce Europe’s leadership in the global semiconductor market.

Disclaimer

The acquisition and operation of the NanoIC pilot line are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programmes (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland, and Romania. For more information, visit nanoic-project.eu.

This article is based on the comment published in Nature Reviews Electrical Engineering (Volume 1 | December 2024 | 764–765 | 764).

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