European Processor Initiative: Project Completion

The European Processor Initiative Showcases Advancements in Sovereign Chip Technology

The European Processor Initiative recently concluded its project, highlighting significant progress in sovereign chip technology for supercomputing and artificial intelligence (AI) during a final review in Luxembourg.

Consisting of 27 partners and funded by the EuroHPC Joint Undertaking, as well as Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland, the European Processor Initiative successfully wrapped up its project four months ago and underwent a comprehensive review in Luxembourg.

During the final review, representatives from the partner companies presented their work to the reviewers and EuroHPC JU staff. Apart from the standard project review process, a special item was included in the schedule.

The review provided a unique opportunity for the project consortium to showcase their achievements, particularly in the development of two processor families – the Arm-based GPP by SiPearl and the European processor accelerator EPAC. To demonstrate these advancements, two types of demonstrations were organized for the reviewers and EuroHPC JU.

EPAC Demo

Leading the EPAC stream, Filippo Mantovani and his team showcased five different demos to the EuroHPC JU staff and reviewers. These demos included a full HPC cluster on the VEC accelerator, the EPAC 1.5 test chip as an accelerator utilizing the real EPAC 1.5 chip as a RISC-V accelerator connected to an Arm host via PCI Express, Kalray KVX demonstrating optimized FFT kernels on their KVX accelerator, Menta showcasing optimization work on their European EDA tool for large eFPGAs, and ZeroPoint memory compression (DenseMem) on EPAC 1.5. Mantovani expressed his excitement at demonstrating the ability to integrate RISC-V into a full HPC software stack, emphasizing the lasting contribution of EPI to the open-hardware ecosystem after four years of the SGA2 project phase.

The second processor family, Rhea1, made its world premiere in Luxembourg. The demo showcased Rhea1 silicon running a complete HPC software stack shortly after the first silicon was received from the foundry and packaging. This article provides additional information on the bring-up process following Rhea1’s return from the foundry.

SiPearl’s Rhea1 Bring-Up: Transitioning European Ambition into Reality

In May 13, 2026, SiPearl’s R&D center in Grenoble, France, received the first shipment of Rhea1 CPUs ever manufactured. This marked a significant moment for the engineers who dedicated years to defining the architecture, designing the silicon, verifying logic gates, and preparing the software stack. Rhea1 represents one of Europe’s most ambitious endeavors in designing a sovereign high-performance, energy-efficient processor for supercomputing and AI.

Developed by SiPearl as part of the European Processor Initiative consortium, Rhea1 is Europe’s first-generation CPU designed to power exascale European supercomputers. With 80 Arm Neoverse V1 compute cores, four stacks of High Bandwidth Memory (HBM), four DDR memory controllers, 104 lanes of PCIe Gen5 interface, and other advanced HPC technologies, Rhea1 stands as the most sophisticated server processor ever developed in Europe.

While designing the processor was a remarkable achievement, bringing it to life posed a different challenge. The arrival of the first silicon marked the beginning of the bring-up process, where years of architecture, hardware design, firmware, and software preparation transitioned into reality through measurements and engineering validations.

The bring-up process progressed rapidly, with SiPearl’s teams achieving various milestones within a few weeks, including first power-on, first clocks, first firmware, first memory access, first PCIe connections, Linux booting across all 80 cores, and the execution of initial HPC benchmarks. This accelerated pace of development showcased the convergence of years of engineering effort towards delivering the first production-ready European HPC processor.

A key factor contributing to this speed was SiPearl’s iterative strategy, which prioritized functionality early on, enabling immediate software integration and continuous improvement based on real hardware feedback. This approach allowed hardware validation, firmware development, Linux integration, and benchmark optimization to progress concurrently.

As of July 20, 2026, the bring-up process is ongoing, with a focus on performance characterization, feature validation, firmware and software optimization, memory subsystem tuning, and unlocking the processor’s full capabilities. Industry-standard HPC benchmarks such as STREAM and HPL are being conducted to validate the computing power and overall hardware and software stack performance. The first comprehensive performance results are expected later this year, marking a significant milestone towards deployment in production.

Upon completion of validation, Rhea1 will be delivered to Bull for integration into computing clusters that will equip JUPITER, the first European exascale supercomputer owned by EuroHPC JU and operated by the Jülich Supercomputing Centre in Germany. This deployment will represent Rhea1’s first real-world customer integration, with general availability slated for late 2026.

Beyond the technical achievements, the bring-up process highlights Europe’s capability not only in designing cutting-edge HPC processors but also in managing manufacturing, integration, and rapid commissioning. It underscores the strength of SiPearl and its EPI partners in delivering strategic technologies for future European supercomputing and AI infrastructure.

Goal: EU Sovereignty

The successful demos and the ongoing bring-up process of Rhea1 signify the fulfillment of EPI’s primary objective. The project aimed to establish a consortium that collaborates on building a European low-power microprocessor, enhancing Europe’s digital sovereignty. While EPI has concluded, other sister projects within the EuroHPC JU’s portfolio and European initiatives, involving many EPI partners, continue to strengthen Europe’s position in the digital landscape, building upon the research and work initiated by EPI.

About EPI

The European Processor Initiative has received funding from the European High Performance Computing Joint Undertaking under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). Supported by the European Union’s Horizon 2020 research and innovation program and contributions from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

Kindly note, this article will also be featured in the 27th edition of our quarterly publication.